A 2 to 1 multiplexer latch is implementable with bipolar integrated circuit design using emitter coupled logic. A mux latch (multiplexer/latch combination) is a standard latch function used in the design of digital logic, and especially in the design of computers. It latches a piece of data in a given state. The latch part of the mux latch holds data when the clock port is held in a given state and it transmits data when the clock pulse is switched to the opposite state. The clock port is generally controlled by a master system clock generated and distributed in different parts of a system.
The multiplexer part of the mux latch is a logic element that accepts data from two places and, under the control of a select port, decides which of the two pieces of data to transmit from the output of the latch. The 2 to 1 mux latch, therefore, accepts data from two sources, and under control of both the clock and the select ports, transmits one of the pieces of data from its output port, or latches the data.
Emitter coupled logic refers to a method of creating a digital logic function using bipolar transistors wired as a differential amplifier with an emitter follower used as an output buffer. An advantage of emitter coupled logic is its high speed, but this comes at a cost of increased power dissipation. Anything done to reduce the power dissipation increases the usefulness of the emitter coupled logic circuitry. One method to reduce the power drain has been to simply lower the supply voltage. However, this approach would not permit the use of 2 to 1 mux latches in the present art.
Another way to reduce the power dissipation is to decrease the number of transistors used for a logic function. In the prior art, a total of four latches are connected to a single clock stage and a single select stage, and receive their clock and select signals from these stages. Each of the four latches has three levels of series gating. Therefore, the voltage supply has to be large enough to support these three levels of gating in order for the circuit to be used. By reducing the number of levels of series gating, a reduced power drain can be achieved. Attempts in the prior art to create the 2 to 1 mux latch function with two levels of series gating have sacrificed the advantageous speed of the device.
It is therefore an object of the present invention to provide a 2 to 1 mux latch function using ECL circuitry with two levels of series gating, without sacrificing the speed advantages of circuits using three levels of series gating.